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DG528/529
Vishay Siliconix
Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers
FEATURES
D D D D D Low rDS(on): 270 W 44-V Power Supply Rating On-Board Address Latches Break-Before-Make Low Leakage--ID(on): 30 pA
BENEFITS
D D D D Improved System Accuracy Microporcessor Bus Compatible Easily Interfaced Reduced Crosstalk
APPLICATIONS
D D D D Data Acquisition Systems Automatic Test Equipment Avionics and Military Systems Medical Instrumentation
DESCRIPTION
The DG528 is an 8-channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (A0, A1, A2). DG529, a 4-channel dual analog multiplexer, is designed to connect one of four differential inputs to a common differential output as determined by its 2-bit binary address (A0, A1) logic. applications. Break-before-make switching action protects against momentary shorting of the input signals. The DG528/529 are built on the improved PLUS-40 CMOS process. A buried layer prevents latchup.
These analog multiplexers have on-chip address and control latches to simplify design in microprocessor based
The on chip TTL-compatible address latches simplify digital interface design and reduce board space in data acquisition systems, process controls, avionics, and ATE.
FUNCTIONAL BLOCK DIAGRAMS AND PIN CONFIGURATIONS
DG528
Dual-In-Line A0 WR A0 EN V- S1 S2 S3 S4 D 1 2 3 4 5 6 7 8 9 Latches Decoders/Drivers 18 17 16 15 14 13 12 11 10 RS A1 A2 GND V+ S5 S6 S7 S8 9 S4 EN V- S1 S2 S3 4 5 6 7 8
DG528
PLCC WR A1 NC RS WR A0 18 A2 17 GND 16 V+ 15 S5 14 S6 S3a 10 11 12 13 S8 NC S7 D S4a Da EN V- S1a S2a 1 2 3 4 5 6 7 8 9
DG529
Dual-In-Line RS A1 GND V+ S1b S2b S3b S4b Db
18 17 Latches Decoders/Drivers 16 15 14 13 12 11 10
3
2
1
20 19
Latches Decoders/Drivers
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DG528/529
Vishay Siliconix
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLE
A2 A1 A0 EN WR RS
DG528
On Switch A0 EN
TRUTH TABLE
WR RS
DG529
On Switch
8-Channel Single-Ended Multiplexer
Differential 4-Channel Multiplexer
Latching
X X X X 1 Maintains previous switch condition
Latching
X X 1 Maintains previous switch condition
Reset
X X X X X 0 None (latches cleared)
Reset
X X X 0 None (latches cleared)
Transparent Operation
X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 None 1 2 3 4 5 6 7 8
Transparent Operation
X 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 None 1 2 3 4
Logic "0" = VAL v 0.8 V Logic "1" = VAH w 2.4 V X = Don't Care
ORDERING INFORMATION
Temp Range
0 to 70_C -25 to 85_C 18-Pin CerDIP 18 Pi C DIP -55 to 125 C 55 125_C
DG528
Part Number
DG528CJ DG528DN DG528BK DG528AK DG528AK/883 5962-8768901VA
ORDERING INFORMATION
Temp Range
0 to 70_C -25 to 85_C 18-Pin CerDIP -55 to 125_C
DG529
Part Number
DG529CJ DG529BK DG529AK/883
Package
18-Pin Plastic DIP 20-Pin PLCC
Package
18-Pin Plastic DIP
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to V- V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2 V to (V+) +2 V or 30 mA, whichever occurs first Current (Any Terminal Except S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Storage Temperature (AK, BK Suffix) . . . . . . . . . . . . . . -65 to 150_C (CJ, DN Suffix) . . . . . . . . . . . . . . -65 to 125_C Power Dissipation (Package)b 18-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 18-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 20-Pin PLCCe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
Notes: a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. Derate 6.3 mW/_C above 75_C. d. Derate 1.2 mW/_C above 75_C. e. Derate 10 mW/_C above 75_C.
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Document Number: 70068 P-32167--Rev. C, 15-Nov-93
DG528/529
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance Greatest Change in rDS(on) Between Channelsf Source Off Leakage Current Drain Off Leakage Current Lk C t VANALOG rDS(on) DrDS(on) IS(off) VD = 10 V, IS = -200 mA -10 V < VS < 10 V VEN = 0 V, VS = "10 V VD = #10 V VEN = 0 V VD = "10 V VS = #10 V DG528 DG529 DG528 DG529 Full Room Full Room Room Full Room Full Room Full Room Full Room Full 270 6 "0.005 "0.015 "0.008 "0.03 "0.015 -1 -50 -10 -200 -10 -100 -10 -200 -10 -100 1 50 10 200 10 100 10 200 10 100 -5 -50 -20 -200 -20 -100 -20 -200 -20 -100 5 50 20 200 20 100 20 200 20 100 nA A -15 15 400 500 -15 15 450 550 V W %
A Suffix
-55 to 125_C
B, C, D Suffix
-40 to 85_C
Symbol
V+ = 15 V, V- = -15 V, WR = 0 RS = 2.4 V, VIN = 2.4 V, 0.8 mFf
Tempb
Typc
Mind
Maxd
Mind Maxd
Unit
ID(off)
Drain On Leakage Current Lk C t
ID(on)
VS = VD = 10 V VEN = 2 4 V 2.4
Digital Control
Logic Input Current IAH Input Voltage High Logic Input Current Input Voltage Low IAL VA = 15 V VEN = 0 V, 2.4 V, VA = 0 V RS = 0 V, WR = 0 V VA = 2.4 V Room Hot Room Hot Room Hot -0.002 0.006 -0.002 -10 -30 -10 -30 10 30 -10 -30 -10 -30 10 30 mA A
Dynamic Characteristics
Transition Time Break-Before-Make Interval EN and WR Turn-On Time EN and WR Turn-Off Time Charge Injection tTRANS tOPEN tON(EN, WR) tOFF(EN, WR) Q See Figure 5 See Figure 4 See Figures 6 and 7 See Figures 6 and 8 VS = 0 V, Ry = 0 W CL = 10 mF VEN = 0 V, RL = 1 kW Off Isolation Logic Input Capacitance Source Off Capacitance OIRR Cin CS(off) CD(off) CL = 15 pF VS = 7 VRMS, f = 500 kHz f = 1 MHz VEN = 0 V, VS = 0 V f = 140 kHz VEN = 0 V VD = 0 V f = 140 kHz DG528 DG529 Room Room Room Room Room 68 2.5 5 pF F 25 12 dB Room Room Room Room Room 0.6 0.2 1 0.4 4 1.5 1 pC ms 1
Drain Off Capacitance
Minimum Input Timing Requirements
Write Pulse Width AX , EN Setup Time AX , EN Hold Time Reset Pulse Width tW tS tH tRS VS = 5 V, See Figure 3 Full Full Full Full 300 180 30 500 300 180 30 500 ns
Document Number: 70068 P-32167--Rev. C, 15-Nov-93
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DG528/529
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Power Supplies
Positive Supply Current Negative Supply Current I+ I- VEN = 0 V, VA = 0 Room Room -1.5 2.5 -1.5 2.5 mA
A Suffix
-55 to 125_C
B, C, D Suffix
-40 to 85_C
Symbol
V+ = 15 V, V- = -15 V, WR = 0 RS = 2.4 V, VIN = 2.4 V, 0.8 mFf
Tempb
Typc
Mind
Maxd
Mind Maxd
Unit
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
rDS(on) vs. VD and Power Supply
TA = 25_C 400 "7.5 V I S, I D (pA) -20 ID(off) 300 "10 V IS(off) 0
Leakage Currents vs. Analog Voltage
ID(on)
500 r DS(on) Drain-Source On-Resistance ( W ) -
200
"15 V
-40 "15 V Supplies TA = 25_C
"20 V 100 -20 -15 -10 -5 0 5 10 15 20 VD - Drain Voltage (V) -60 -15 -10 -5 0 5 10 15 VANALOG - Analog Voltage (V)
Input Switching Threshold vs. V+ and V- Supply Voltages
2.5 TA = 25_C 2.0 3 I+, I- (mA) V T (V) 1.5 4
Supply Currents vs. Toggle Frequency
I+ 2
1.0
0.5
1
I-
0 0
0 "5 "10 "15 "20 1k 10 k 100 k 1M V+, V- Positive and Negative Supplies (V) Toggle Frequency (Hz) Document Number: 70068 P-32167--Rev. C, 15-Nov-93
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DG528/529
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+ GND VREF V+ EN V+ V- AX V+ V- WR V+ V- RS V- V+ CLK RESET DO QO V- V+ Dn Qn V- V+ V- D Latches Level Shift Decode V- Sn S1
V+
FIGURE 1.
DETAILED DESCRIPTION
The internal structure of the DG528/DG529 includes a 5-V logic interface with input protection circuitry followed by a latch, level shifter, decoder and finally the switch constructed with parallel n- and p-channel MOSFETs (see Figure 1). Following the latches the QX signals are level shifted and decoded to provide proper drive levels for the CMOS switches. This level shifting insures full on/off switch operation for any analog signal present between the V+ and V- supply rails.
The logic interface circuit compares the TTL input signal against a TTL threshold reference voltage. The output of the comparator feeds the data input of a D type latch. The level sensitive D latch continuously places the DX input signal on the QX output when the WR input is low, resulting in transparent latch operation. As soon as WR returns high, the latches hold the data last present on the DX input, subject to the minimum input timing requirements.
3V WR 0 tW tS 3V A0, A1, (A2) EN 0 tH 50%
The EN pin is used to enable the address latches during the WR pulse. It can be hard-wired to the logic supply or to V+ if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. The RS pin is used as a master reset. All latches are cleared regardless of the state of any other latch or control line. The WR pin is used to transfer the state of the address control lines to their latches, except during a reset or when EN is low (see Truth Tables).
3V RS 0 tRS tOFF (RS) Switch Output VO 80% 0 50%
80% 80%
FIGURE 2.
FIGURE 3.
Document Number: 70068 P-32167--Rev. C, 15-Nov-93
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DG528/529
Vishay Siliconix
TEST CIRCUITS
+15 V V+ All S and Da +5 V tr <20 ns tf <20 ns 50% 0V
+2.4 V
RS EN
Logic Input
3V
DG528 DG529
A0, A1, (A2) GND 50 W WR Db, D V- 300 W 35 pF Switch Output VO 0V tOPEN VO VS 80%
-15 V
FIGURE 4. Break-Before-Make
+15 V RS EN S2 - S7 A0 A1 A2 GND 50 W -15 V Switch Output +15 V +2.4 V RS EN A0 A1 GND 50 W -15 V V+ S1b S1a - S4a, Da S2b and S3b #10 V VO 0V 10% VS8 tTRANS S1 ON VO 35 pF tTRANS S8 ON tr <20 ns tf <20 ns 50% 0V 35 pF VS1 90% V+ S1 "10 V
+2.4 V
DG528
WR V-
S8 D 300 W
#10 V VO
Logic Input
3V
DG529
WR V-
S4b Db 300 W
"10 V
FIGURE 5. Transition Time
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Document Number: 70068 P-32167--Rev. C, 15-Nov-93
DG528/529
Vishay Siliconix
TEST CIRCUITS
+15 V V+ RS EN A0 A1 A2 GND 50 W WR V- S1 -5V
+2.4 V
DG528
S2 - S8
D 300 W
VO 35 pF Logic Input
3V 50% 0V tON(EN) 0V
tr <20 ns tf <20 ns
-15 V
tOFF(EN)
+15 V V+ RS EN A0 A1 GND 50 W WR V- 300 W -15 V S1b -5V Switch Output VO VO 90%
+2.4 V
DG529
S1a - S4a, Da S2b - S4b Db VO 35 pF
FIGURE 6. Enable tON/tOFF Time
+15 V V+
+2.4 V
EN A0, A1, (A2)
S1 or S1b Remaining Switches
+5 V WR
3V 50% 0V VO tON(WR) Switch Output 20% 0V
RS
DG528
Db, D V- 300 W -15 V 35 pF VO
DG529 WR GND
FIGURE 7. Write Turn-On Time tON(WR)
Document Number: 70068 P-32167--Rev. C, 15-Nov-93
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DG528/529
Vishay Siliconix
TEST CIRCUITS
+15 V
+2.4 V
EN A0, A1, (A2)
V+
S1 or S1b Remaining Switches
+5 V
3V RS 0V tOFF(RS) VO VO 35 pF Switch Output 0V 80% 50%
RS GND
DG528 DG529
WR
Db, D V- 300 W -15 V
FIGURE 8. Reset Turn-Off Time tOFF(RS)
+15 V V+ S1 "15 V Analog Inputs
Data Bus
A0, A1, A2 , EN
Processor System Bus
DG528
RESET +5 V WRITE Address Bus Address Decoder D V- - 15 V WR S8 RS
Analog Output
FIGURE 9. Bus Interface
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Document Number: 70068 P-32167--Rev. C, 15-Nov-93
DG528/529
Vishay Siliconix
APPLICATION HINTSa
V+ Positive Supply Voltage (V)
20 15b 8c
V- Negative Supply Voltage (V)
-20 -15 -8 (min)
VIN Logic Input Voltage VINH(min)/VINL(max) (V)
2.4/0.8 2.4/0.8 2.4/0.8
VS or VD Analog Voltage Range (V)
"20 "15 "8
Notes: a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing. b. Electrical Parameter Chart based on V+ = 15 V, VL = 5 V, VR = GND. c. Operation below "8 V is not recommended.
The DG528/DG529 minimize the amount of interface hardware between a microprocessor system bus and the analog system being controlled or measured. The internal TTL compatible latches give these multiplexers write-only memory, that is, they can be programmed to stay in a particular switch state (e.g., switch 1 on) until the microprocessor determines it is necessary to turn different switches on or turn all switches off (see Figure 9).
During system power-up, RS would be low, maintaining all eight switches in the off state. After RS returned high the DG528 maintains all switches in the off state. When the system program performs a write operation to the address assigned to the DG528, the address decoder provides a CS active low signal which is gated with the WRITE (WR) control signal. At this time the data on the DATA BUS (that will determine which switch to close) is stabilizing. When the WR signal returns to the high state, (positive edge) the input latches of the DG528 save the data from the DATA BUS. The coded information in the A0, A1, A2 and EN latches is decoded and the appropriate switch is turned on.
The input latches become transparent when WR is held low; therefore, these multiplexers operate by direct command of the coded switch state on A2, A1, A0. In this mode the DG528 is identical to the popular DG508A. The same is true of the DG529 versus the popular DG509A.
The EN latch allows all switches to be turned off under program control. This becomes useful when two or more DG528s are cascaded to build 16-line and larger multiplexers.
Document Number: 70068 P-32167--Rev. C, 15-Nov-93
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Legal Disclaimer Notice
Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000 Revision: 08-Apr-05
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